As an arrangement of a conventional matrix-type image display device such as a liquid crystal display device, an arrangement shown in FIG. 13 has been well known. In this image display device, a plurality of data signal lines 51 and a plurality of scanning signal lines 52 are provided so as to be orthogonal to each other on one of a pair of substrates or the both. Around each intersection of the signal lines 51 and 52, a pixel (not shown) is provided. The data signal lines 51 are connected to a data signal line driving circuit 53, so that data signals (image signals) to be applied to the pixels are supplied from the data signal line driving circuit 53 to the data signal lines 51. On the other hand, the scanning signal lines 52 are connected to a scanning signal line driving circuit 54, so that scan signals for selecting pixels to receive the data signals supplied to the data signal lines 51 are supplied from the scanning signal line driving circuit 54 to the scanning signal lines 52.
A schematic arrangement of the data signal line driving circuit 53 is shown in FIG. 14. The data signal line driving circuit 53 incorporates a scanning circuit 55 for sequentially outputting pulse signals at fixed intervals, and a sample-and-hold circuit (hereinafter referred to as S/H circuit) 56 for sampling and outputting the data signals inputted thereto from outside in response to signals supplied from the scanning circuit 55. The scanning signal line driving circuit 54 has substantially the same arrangement, wherein usually a buffer circuit is used instead of the S/H circuit 56.
Any of the driving circuits 53 and 54 requires the scanning circuit 55. There are two types of the scanning circuit 55, namely, (1) one type using a shift register, and (2) the other type using a decode circuit, a multiplexer circuit, or the like, for conducting simple logical computations with respect to a plurality of pulse signals supplied thereto so as to output pulse signals.
As an example of the latter type (2), a circuit structure in the case where a decode circuit is used therein is shown in FIG. 15. Note that the figure is simplified for purposes of illustration, with a small number of signal lines or the like being shown.
The scanning circuit 55 has scan control signal lines (hereinafter referred to as SCS lines) 61 composed of signal lines 61.sub.1 through 61.sub.8, and a pulse generating circuit 62 composed of circuits 62.sub.1 through 62.sub.16. Each pulse generating circuit 62 conducts logical computations with respect to signals supplied from the SCS lines 61 and outputs the computation results. Each pulse generating circuit 62 has m (m=4 in this example) input terminals, and the n'th (n.ltoreq.m) input terminal is supplied with a signal from either the signal line 61.sub.2n-1 or the signal line 61.sub.2n of the SCS lines 61. In addition, combinations of scan control signals supplied to the pulse generating circuits 62.sub. through 62.sub.16 differ from one another. By doing so, 2.sup.4 (=16) pulse signals at most are controlled.
FIG. 16 is a timing chart illustrating examples of signal waveforms applied to respective parts of the scanning circuit 55. The scan control signals SCS61 through SCS.sub.68 are supplied to the SCS lines 61.sub.1 through 61.sub.8, respectively. To be more specific, supplied to the signal lines 61.sub.2n-1 and the signal line 61.sub.2n during a scanning period are signals which have a phase difference of 180.degree. from each other and which have cycles and pulse widths 2.sup.n times and 2.sup.n-1 times as great as a reference time interval t1, respectively. By thus arranging, one combination of the scan control signals supplied to the pulse generating circuits 62.sub.1 through 62.sub.16 is switched to another combination per one reference time interval t1, and one pulse signal is selected among pulse signals PS.sub.1 through PS.sub.16 in accordance with the combination so as to be supplied to output signal lines 63.sub.1 through 63.sub.16.
Incidentally, display in accordance with high-definition image signals has recently been demanded with respect to the matrix-type image display device, and this has led to development of, for example, SVGA, XGA, and high-definition televisions. In such cases, as the numbers of the data signal lines 51 and the scanning signal lines 52 increase, the SCS lines 61 and the input terminals of the pulse generating circuits 62 accordingly increase.
The increase in the number of the input terminals of the pulse generating circuits 62 causes an increase in crossings of the SCS lines 61 and wires from the SCS lines 61 to the input terminals of the pulse generating circuits 62. As a result, parasitic capacitances of the SCS lines 61 increase.
Besides, the number of the SCS lines 61 itself increases, thereby, in combination with the increase in the parasitic capacitances, causing an increase in power consumption by the scanning circuit 55 as a whole.
Furthermore, the increase in the number of the SCS lines 61 and the increase in the number of the input terminals of the pulse generating circuits 62 cause the scanning circuit 55 to become bulky, thereby resulting in that miniaturization of the circuit becomes difficult.